The present disclosure relates to a method for bonding substrates, and particularly, to a method of bonding substrates while minimizing stress induced by a mismatch in the coefficients of thermal expansion (CTE's) between the substrates.
A first substrate can be bonded to a second substrate by employing an array of solder material portions. For example, in a solder bonding employing bonding pads, each solder material portion contacts a bonding pad on the semiconductor chip and another bonding pad on another semiconductor chip or the packaging substrate. Each bonding pad is a contiguous metal pad typically formed out of the last metal layer of a metal interconnect structure during a semiconductor manufacturing sequence. Each bonding pad is large enough to accommodate the bottom portion of a solder material portion. Typically, an array of solder material portions can be employed to provide input/output (I/O) connections between the semiconductor chip and another semiconductor chip or a packaging substrate.
Connections employing an array of solder material portions, such as C4 balls or any other type of solder balls, are susceptible to mechanical stress created by a mismatch in the coefficients of thermal expansion (CTE's) between the semiconductor chip and the other semiconductor chip or the packaging substrate. Such mechanical stress may cause cracks in the solder material portions, back-end-of-lines in chips, or the semiconductor chip(s), causing the semiconductor chip(s) to fail during flip chip assembly process and/or usage.
The problem of mechanical stress caused by the mismatch between CTE's are exacerbated when an organic substrate is employed for a packaging substrate because the mismatch of CTE's is greater between organic substrates and semiconductor substrates than between ceramic substrates and semiconductor substrates. When an organic substrate is used as a packaging substrate for a fine pitch flip chip assembly, substrate warpage can occur in the conventional reflow process during which solder balls reflow. This warpage can result in non-wetting of solder bumps and/or bridging between solder bumps, thereby decreasing the assembly yield.
In general, organic substrates expand and contract more than silicon chips. For example, a silicon chip has a CTE of about 2.6 p.p.m./° C., and an organic substrate has a CTE of about 17 p.p.m./° C. Such a mismatch between CTE's can create thermally-induced stress and strain in a bonded flip-chip structure during the flip chip assembly process. Thermally-induced stress and strain in the flip-chip structure during a reflow process often results in a failure of back-end-of-line (BEOL) interconnect structures.
Warpage of organic substrates and thermally-induced stress and strain increase as the size of an organic substrate increases, which is common for high performance chips and components. U.S. Pat. No. 7,235,886 to Chandran et al. discloses a method to reduce elongation mismatch by separately heating the chip and the second substrate prior to bonding. According to this method, a die is detached from a heater and placed onto a packaging substrate after the die and the second substrate reach different steady state temperatures. Because the die is detached from a bonder head including a heater at the time of bonding, the temperature of the die decreases quickly after the die detaches from the bonder head. As a result, reflow of solder joint is non-existent or limited in this method. Further, this method does not provide a mechanism for overcoming solder non-wet issues and solder bridging problems due to solder height variation in the array of solder material portions and in any other conductive bonding structure contacting the array of solder material portions, and substrate warpage. Organic substrates always have a certain amount of initial warpage even at room temperature due to stacking of multi-layers of metals and polymers.
In light of the above, there exists a need to provide a reliable flip chip joining method that avoids stress and strain and warpage issues due to mismatch in CTE, while at the same time ensuring that solid solder joints are formed and all solder materials are wetted to provide reliable electrical connection between a semiconductor chip and a packaging substrate.